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cy7c1021bnv33 64 k 16 static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-06433 rev. *d revised october 12, 2011 64 k 16 static ram features 3.3 v operation (3.0 v?3.6 v) high speed ? t aa = 15 ns cmos for optimum speed/power low active power ? 576 mw (max) low cmos standby power ? 1.80 mw (max) automatic power-down when deselected independent control of upper and lower bits available in 44-pin tsop ii and 400-mil soj available in a 48-ball mini bga package functional description the cy7c1021bnv33 [1] is a high-performance cmos static ram organized as 65,536 words by 16 bits. this device has an automatic power-down feature that significantly reduces power consumption when deselected. writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location specified on the address pins (a 0 through a 15 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 15 ). reading from the device is accomplished by taking chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins will appear on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory will appear on i/o 8 to i/o 15 . see the truth table at the back of this data sheet for a complete description of read and write modes. the input/output pins (i/o 0 through i/o 15 ) are placed in a high-impedance state when the device is deselected (ce high), the outputs are disabled (oe high), the bhe and ble are disabled (bhe , ble high), or during a write operation (ce low, and we low). the cy7c1021bnv33 is available in 400-mil-wide soj, standard 44-pin tsop type ii, and 48-ball mini bga packages. note 1. for guidelines on sram system design, pl ease refer to the ?system de sign guidelines? cypress app lication note, available on t he internet at www.cypress.com . [+] feedback
cy7c1021bnv33 document #: 001-06433 rev. *d page 2 of 17 64k x 16 ram array i/o 0 ?i/o 7 row decoder a 7 a 6 a 5 a 4 a 3 a 0 column decoder a 9 a 10 a 11 a 12 a 13 a 14 a 15 sense amps data in drivers oe a 2 a 1 i/o 8 ?i/o 15 ce we ble bhe a 8 logic block diagram selection guide -15 maximum access time (ns) 15 maximum operating current (ma) 160 maximum cmos standby current (ma) 0.5 [+] feedback
cy7c1021bnv33 document #: 001-06433 rev. *d page 3 of 17 contents pin configurations ........................................................... 4 maximum ratings ............................................................. 5 operating range ............................................................... 5 electrical characteristics ................................................. 5 capacitance ...................................................................... 5 ac test loads and waveforms ....................................... 6 switching characteristics ................................................ 7 data retention characteristics ....................................... 8 data retention waveform ................................................ 8 switching waveforms ...................................................... 9 truth table ...................................................................... 11 ordering information ...................................................... 12 ordering code definitions ..... .................................... 12 package diagrams .......................................................... 13 acronyms ........................................................................ 15 document conventions ................................................. 15 units of measure ....................................................... 15 document history page ................................................. 16 sales, solutions, and legal information ...................... 17 worldwide sales and design s upport ......... .............. 17 products .................................................................... 17 psoc solutions ......................................................... 17 [+] feedback
cy7c1021bnv33 document #: 001-06433 rev. *d page 4 of 17 pin configurations we 1 2 3 4 5 6 7 8 9 10 11 14 31 32 36 35 34 33 37 40 39 38 top view soj / tsop ii 12 13 41 44 43 42 16 15 29 30 v cc a 15 a 14 a 13 a 12 nc a 4 a 3 oe v ss a 5 i/o 15 a 2 ce i/o 2 i/o 0 i/o 1 bhe nc a 1 a 0 18 17 20 19 i/o 3 27 28 25 26 22 21 23 24 nc v ss i/o 6 i/o 4 i/o 5 i/o 7 a 6 a 7 ble v cc i/o 14 i/o 13 i/o 12 i/o 11 i/o 10 i/o 9 i/o 8 a 8 a 9 a 10 a 11 mini bga top view ble oe bhe we a 0 a 4 a 1 a 2 ce v ss i/o 0 a 3 i/o 8 i/o 10 i/o 9 a 6 a 5 i/o 2 i/o 1 i/o 4 i/o 11 nc a 7 i/o 3 v cc nc v ss v cc i/o 12 nc nc i/o 14 i/o 13 i/o 7 a 8 a 15 a 14 i/o 6 i/o 6 i/o 15 nc a 12 a 13 nc nc a 9 a 10 a 11 1234 5 6 a b c d e f g h [+] feedback
cy7c1021bnv33 document #: 001-06433 rev. *d page 5 of 17 maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. storage temperature ................ ............... ?65 c to +150 c ambient temperature with power applied ........... ............... ............... ?55 c to +125 c supply voltage on v cc to relative gnd [2] ................................?0.5 v to +4.6 v dc voltage applied to outputs in high z state [2] ................................. ?0.5 v to v cc + 0.5 v dc input voltage [2] ............................. ?0.5 v to v cc + 0.5 v current into outputs (low) .... .................................... 20 ma static discharge voltage (per mil-std-883, method 3015) .............. ............ > 2001 v latch-up current ................................................... > 200 ma operating range range ambient temperature v cc industrial ?40 c to +85 c 3.3 v ? 10% electrical characteristics over the operating range parameter description test conditions -15 unit min max v oh output high voltage v cc = min, i oh = ?4.0 ma 2.4 ? v v ol output low voltage v cc = min, i ol = 8.0 ma ? 0.4 v v ih input high voltage 2.2 v cc + 0.3 v v v il input low voltage [2] ?0.3 0.8 v i ix input load current gnd < v i < v cc ?1 +1 ? a i oz output leakage current gnd < v i < v cc , output disabled ?1 +1 ? a i cc v cc operating supply current v cc = max, i out = 0 ma, f = f max = 1/t rc ? 160 ma i sb1 automatic ce power down current ?ttl inputs max v cc , ce > v ih , v in > v ih or v in < v il , f = f max ? 40 ma i sb2 automatic ce power down current ?cmos inputs max v cc , ce > v cc ? 0.3 v, v in > v cc ? 0.3 v or v in < 0.3 v, f = 0 ? 500 ? a capacitance parameter [3] description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz 6 pf c out output capacitance 8 pf notes 2. minimum voltage is ?2.0 v for pulse durations of less than 20 ns. 3. tested initially and after any design or process changes that may affect these parameters. [+] feedback
cy7c1021bnv33 document #: 001-06433 rev. *d page 6 of 17 ac test loads and waveforms 90% 10% 3.0 v gnd 90% 10% all input pulses 3.3 v output 30 pf including jig and scope 3.3 v output 5 pf including jig and scope (a) (b) output r 317 ? r 317 ? r2 351 ? r2 351 ? 167 equivalent to: thvenin equivalent 1.73 v 30 pf rise time: 1 v/ns fall time: 1 v/ns [+] feedback
cy7c1021bnv33 document #: 001-06433 rev. *d page 7 of 17 switching characteristics over the operating range parameter [4] description -15 unit min max read cycle t rc read cycle time 15 ? ns t aa address to data valid ? 15 ns t oha data hold from address change 3 ? ns t ace ce low to data valid ? 15 ns t doe oe low to data valid ? 7 ns t lzoe oe low to low z 0 ? ns t hzoe oe high to high z [5, 6] ? 7 ns t lzce ce low to low z [6] 3 ? ns t hzce ce high to high z [5, 6] ? 7 ns t pu ce low to power-up 0 ? ns t pd ce high to power-down ? 15 ns t dbe byte enable to data valid ? 7 ns t lzbe byte enable to low z 0 ? ns t hzbe byte disable to high z ? 7 ns write cycle [7] t wc write cycle time 15 ? ns t sce ce low to write end 10 ? ns t aw address set-up to write end 10 ? ns t ha address hold from write end 0 ? ns t sa address set-up to write start 0 ? ns t pwe we pulse width 10 ? ns t sd data set-up to write end 8 ? ns t hd data hold from write end 0 ? ns t lzwe we high to low z [6] 3 ? ns t hzwe we low to high z [5, 6] ? 7 ns t bw byte enable to end of write 9 ? ns notes 4. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 v, input pulse levels of 0 to 3 .0 v, and output loading of the specified i ol /i oh and 30-pf load capacitance. 5. t hzoe , t hzbe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in part (b) of ac test loads and waveforms on page 6 . transition is measured ? 500 mv from steady-state voltage. 6. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 7. the internal write time of the memory is defined by the overlap of ce low, we low and bhe / ble low. ce , we and bhe / ble must be low to initiate a write, and the transition of these signals can terminate the write. t he input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. [+] feedback
cy7c1021bnv33 document #: 001-06433 rev. *d page 8 of 17 data retention characteristics over the operating range (l version only) parameter description conditions [8] min max unit v dr v cc for data retention 2.0 ? v i ccdr data retention current v cc = v dr = 2.0 v, ce > v cc ? 0.3 v, v in > v cc ? 0.3 v or v in < 0.3 v ? 100 ? a t cdr [9] chip deselect to data retention time 0 ? ns t r [10] operation recovery time 15 ? ns data retention waveform 3.0 v 3.0 v t cdr v dr > 2 v data retention mode t r ce v cc notes 8. no input may exceed v cc + 0.5 v. 9. tested initially and after any design or proces s changes that may affect these parameters. 10. t r < 3 ns for the -12 and -15 speeds. t r < 5 ns for the -20 and slower speeds. [+] feedback
cy7c1021bnv33 document #: 001-06433 rev. *d page 9 of 17 switching waveforms figure 1. read cycle no. 1 [11, 12] figure 2. read cycle no. 2 (oe controlled) [12, 13] previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzbe t pd high oe ce icc isb impedance address data out v cc supply t dbe t lzbe t hzce bhe , ble current i cc i sb notes 11. device is continuously selected. oe , ce , bhe and/or bhe = v il . 12. we is high for read cycle. 13. address valid prior to or coincident with ce transition low. [+] feedback
cy7c1021bnv33 document #: 001-06433 rev. *d page 10 of 17 figure 3. write cycle no. 1 (ce controlled) [14, 15] figure 4. write cycle no. 2 (ble or bhe controlled) switching waveforms (continued) t hd t sd t sce t sa t ha t aw t pwe t wc bw data i/o address ce we bhe, ble t t hd t sd t bw t sa t ha t aw t pwe t wc t sce data i/o address bhe ,ble we ce notes 14. data i/o is high impedance if oe or bhe and/or ble = v ih . 15. if ce goes high simultaneously with we going high, the output remains in a high-impedance state. [+] feedback
cy7c1021bnv33 document #: 001-06433 rev. *d page 11 of 17 figure 5. write cycle no. 2 (we controlled, oe low) switching waveforms (continued) t hd t sd t sce t ha t aw t pwe t wc t bw data i/o address ce we bhe , ble t sa t lzwe t hzwe truth table ce oe we ble bhe i/o 0 ?i/o 7 i/o 8 ?i/o 15 mode power h x x x x high z high z power-down standby (i sb ) l l h l l data out data out read - all bits active (i cc ) l h data out high z read - lower bits only active (i cc ) h l high z data out read - upper bits only active (i cc ) l x l l l data in data in write - all bits active (i cc ) l h data in high z write - lower bits only active (i cc ) h l high z data in write - upper bits only active (i cc ) l h h x x high z high z selected, outputs disabled active (i cc ) l x x h h high z high z selected, outputs disabled active (i cc ) [+] feedback
cy7c1021bnv33 document #: 001-06433 rev. *d page 12 of 17 ordering information cypress offers other versions of this ty pe of product in many different configurat ions and features. the following table contai ns only the list of parts that are currently available. for a comp lete listing of all options, visit the cypress website at http://www.cypress.com and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative. cypress maintains a worldwide network of offices, solution cent ers, manufacturer?s representativ es and distributors. to find th e office closest to you, visit us at http://www.cypress.com/ go/datasheet/offices . speed (ns) ordering code package diagram package type operating range 15 cy7c1021bnv33l-15bai 51-85096 48-ball mini bga (7 mm 7 mm) industrial cy7c1021bnv33l-15zxi 51-85087 44-pin tsop type ii (pb-free) ordering code definitions please contact local sales representative regarding availability of these parts. temperature range: i = industrial package type: xx = ba or vx or zx ba = 48-ball mini bga vx = 44-pin molded soj (pb-free) zx = 44-pin tsop type ii (pb-free) speed: 15 ns l = low power v33 = voltage range (3 v to 3.6 v) bn = 0.25 m technology 1 = data width 16-bits 02 = 1-mbit density 1 = fast asynchronous sram family technology code: c = cmos 7 = sram cy = cypress c cy 1 - 15 xx 7 02 v33 i 1 bn l [+] feedback
cy7c1021bnv33 document #: 001-06433 rev. *d page 13 of 17 package diagrams figure 6. 48-ball fbga (7 mm 7 mm 1.2 mm) ba48 package outline, 51-85096 figure 7. 44-pin soj (400 mils) v44.4 package outline, 51-85082 51-85096 *i 51-85082 *d [+] feedback
cy7c1021bnv33 document #: 001-06433 rev. *d page 14 of 17 figure 8. 44-pin tsop z44-ii package outline, 51-85087 package diagrams (continued) 51-85087 *d [+] feedback
cy7c1021bnv33 document #: 001-06433 rev. *d page 15 of 17 acronyms document conventions units of measure acronym description bga ball grid array ce chip enable cmos complementary metal oxide semiconductor fbga fine-pitch ball grid array i/o input/output oe output enable soj small outline j-lead sram static random access memory tsop thin small-outline package ttl transistor-transistor logic we write enable symbol unit of measure c degree celsius mhz megahertz a microampere s microsecond ma milliampere mm millimeter mw milliwatt ns nanosecond ? ohm % percent pf picofarad vvolt wwatt [+] feedback
cy7c1021bnv33 document #: 001-06433 rev. *d page 16 of 17 document history page document title: cy7c1021bnv33, 64 k 16 static ram document number: 001-06433 rev. ecn no. issue date orig. of change description of change ** 423847 see ecn nxr new data sheet *a 2897061 03/22/10 aju removed obsolete parts from ordering information table updated package diagrams *b 3109897 12/14/2010 aju added ordering code definitions *c 3103073 03/08/2011 pras updated package diagrams . added acronyms and units of measure . updated in new template. *d 3403051 10/12/2011 aju updated ordering information (removed prune part number cy7c1021bnv33l-15vxi). updated package diagrams . [+] feedback
document #: 001-06433 rev. *d revised october 12, 2011 page 17 of 17 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c1021bnv33 ? cypress semiconductor corporation, 2006-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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